Core8Bit mainboard (in development)

In development. The KiCad project is in progress; there is no final schematic or parts list yet. Values marked "starting value" are a starting point. Open points are marked TBD.

The mainboard replaces the printed base plate and all the wires of the wired build (assembly.md, path A).

Related pages: hardware.md, pinout.md, power.md, bom.md, assembly.md.

Concept
Geometry
Layers
Board blocks
USB-C: charging and OTG
Hard reset
VS1003B MP3 module
Audio
Display
New STM32 signals
Case changes
Files
Open questions

Concept

A two-layer PCB with the same shape as the base plate (base-plate.stl): the same outline, the same holes, the same mounting points. It fits the existing case in place of the base plate.
Front layer (TOP, under the buttons): buttons, sticks and almost all traces.
Back (BOTTOM): all modules sit on pin headers (STM32H7 core board, ESP32 DevKit, amplifier, boosts, charger board, 21 V booster, VS1003B module). The rest of the back is an almost solid ground pour. It shields the display and the front traces from the noisy modules and gives return currents a short path.
As few vias as possible. Front traces run straight to the through-hole pads of the module headers. Use vias mainly to stitch the ground pour.
The modules are removable: flash, test and replace each one separately.

Geometry

Front view, mm, assembly coordinate system (same as base-plate.stl).

Parameter	Value	Comment
Outline	about 122.3 × 135.1 mm, same as the base plate	copy the outline from the STL
Thickness	base plate 1.5 mm; standard PCB 1.6 mm	test-fit the 0.1 mm difference in the case
Button holes	Ø 2.1 mm, 4 per button: D-pad, 2 centre buttons, A/B/X/Y (the D-pad and A/B/X/Y buttons are rotated 45°)	on the PCB these become button pads
Stick mounting	Ø 1.85 mm, 4 holes per stick, 20.4 × 20.4 mm pitch
Speaker wire holes	Ø 5.5 mm at about X ±36, Y −85	on the PCB they can be replaced with wire pads
Amplifier window	24 × 9 mm slot at Y ≈ −66.6	access to the volume trimmers
Corner cut-outs	semicircular, for the case's corner tubes
Module mounting points	base plate posts (see assembly.md)	on the mainboard they become mounting holes and module header positions
VS1003B area	the base plate has a free 37 × 37 mm area with 4 posts (X −55…−18, Y −59…−96)	whether this is the VS1003B area is TBD

Heights: below the board (module side) about 9.4 mm to the back cover; above the board about 10 mm to the front wall. Modules on headers must fit in 9.4 mm including the socket height: use low-profile sockets, or solder the modules straight onto pins.

Layers

Layer	What is on it
TOP (front)	button and stick pads; traces for the buttons (3.3 V + 10 signals), the sticks (3.3 V, GND, 4 axes), the display bus, SPI4, SPI2, USB D+/D−, audio; SMD parts (33 Ω resistors, filters, TUSB320, switches). Free areas are filled with ground
BOTTOM (back)	module sockets; hard reset button; solid GND pour. Power nets (battery, 5 V) run as short, wide traces next to the power modules

Routing rules (starting point):

Route the display RGB bus and CLK over the solid ground of the back, with no breaks in the pour under them.
Route D+/D− as a pair, equal in length, as short as possible.
Keep the analog section (DAC → filters → amplifier) away from the boosts and the display CLK. Connect the audio ground to the common ground at one point ("star").
Do not run the power ground of the boosts and the amplifier under the amplifier input.

Board blocks

Block	What it does	Details
Power	USB-C → diode/ideal diode → charger board ↔ Li-Po; boost #2 → ferrite bead → core board; boost #1 (EN = PE4) → ferrite bead → ESP32, amplifier, 21 V booster	USB-C, power.md
USB data	USB-C D+/D− → 22 Ω → PA11/PA12	USB-C
CC / port mode	TUSB320 in DRP mode	USB-C
OTG power	P-MOSFET switch 5 V → VBUS controlled by a GPIO; charging disabled (CE) during OTG	USB-C
Hard reset	SMD micro button on the back, core board NRST → GND	reset
Display	33 Ω on CLK and the sync lines, solid ground under the bus	display
Buttons, sticks	as today: buttons to 3.3 V (active HIGH), sticks are 3.3 V / GND potentiometers	pinout.md
ESP32	SPI4 as today, + CS pull-up, 33 Ω series resistors on SCK/MOSI/CS (STM32 side) and MISO (ESP32 side)	pinout.md
Audio	DAC → RC filter → mixing with the VS1003B → PAM8406; LC filter on the supply	audio
VS1003B	module on SPI2	VS1003B

USB-C: charging and OTG

One external USB-C port for the whole console. It is used for charging, for OTG (connecting USB devices to the console) and for the PC link.

                      ┌──────────── TUSB320 (DRP) ──── INT / ID ──► STM32 GPIO (TBD)
                      │  CC1, CC2
 USB-C ── VBUS ───────┼──► SS34 (or P-MOSFET ideal diode) ──► charger board input ◄─► Li-Po
   │                  │                                                   │ CE ◄── GPIO / OTG logic (TBD)
   │                  ├──► divider ──► PA9 (VBUS sense)                   ▼
   │                  │                                         boost #2 ─► STM32
   │                  └──◄── P-MOSFET switch ◄── 5 V of the boost #1 rail (PE4)
   │                              ▲ gate ◄── GPIO OTG_EN (TBD)
   │
   └── D+ (A6/B6) ── 22 Ω ──► PA12
       D− (A7/B7) ── 22 Ω ──► PA11

Charging input

The 5 V from the connector's VBUS reaches the charger board input through an SS34 Schottky diode or through a P-MOSFET used as an ideal diode.
The diode stops the voltage from the OTG switch output and from the charger board itself from flowing back into the connector.
An SS34 is simpler but drops about 0.3–0.5 V at forward current. A P-MOSFET ideal diode has almost no loss but is more complex. The choice is TBD.

OTG: power for the connected device

When the console acts as host, the 5 V on VBUS comes from the boost #1 rail through a P-MOSFET load switch. An STM32 GPIO drives the gate (OTG_EN, pin TBD).
Boost #1 runs only while PE4 = HIGH, so OTG works only while the 5 V rail is on.
Charging is disabled during OTG (the charger IC's CE pin). Otherwise the 5 V from the OTG switch reaches the charger input through the diode, and the battery "charges itself" through the boost: a useless circulating current and heat. Whether the chosen charger board has an accessible CE pin, and what drives it (the same OTG_EN or a separate GPIO), is TBD.
Current limiting for the external device (a fuse or a current-limited switch) is TBD.

CC: TUSB320 in DRP mode

A TUSB320 (TI) in DRP mode handles CC1/CC2 (dual-role: the port switches between sink and source by itself).
Do not use fixed resistors: 5.1 kΩ (Rd) on CC makes the port sink-only (no OTG detection); 56 kΩ (Rp) makes it host-only (a PC or charger cannot see the console).
The TUSB320 INT/ID output goes to an STM32 GPIO (pin TBD). The firmware reads it to learn what is connected (a charger/PC or a USB device) and turns on the OTG switch.
The PORT pin sets the mode; the VBUS_DET pin detects VBUS. Take the support circuit (resistors, pull-ups, I2C or not) from the TUSB320 datasheet. The chip variant (TUSB320, TUSB320L/LAI…) is TBD.

Data

D+ → PA12, D− → PA11 through 22 Ω series resistors.
Keep the D+/D− traces equal in length and short, next to each other, over solid ground.
USB-C duplicates D+/D− (A6/B6, A7/B7) for the reversible plug. Join each pair right at the connector.
Important: PA11/PA12 are not broken out to the headers of the core board (see pinout.md). They go to its own "USB" micro-USB jack. How to bring D+/D− from the mainboard to PA11/PA12 (wires to the core board's micro-USB contacts, a micro-USB plug, or something else) is TBD. Do not use the core board's micro-USB jack and the external USB-C at the same time.
The firmware currently supports only USB device mode (MSC "Core8Bit MSC" and the debug CDC). Host (OTG) mode is not implemented in the firmware yet.

PA9: VBUS sensing

PA9 stays the VBUS sense input: the connector's VBUS through a divider (starting value about 2:1, for example 10 kΩ / 20 kΩ, so that 5 V gives ≈ 3.3 V).
This gives reliable charging detection (on the wired build PA9 follows the 5 V rail, see power.md). In OTG mode PA9 also sees 5 V; the firmware must take this into account.
The microphone, earlier planned on PA9 (ADC), moves to another free ADC input. Which one is TBD (candidates: PC5, or PA1 if PA1 is not needed for the wake-up button).

Hard reset

An SMD tactile micro button on the back of the board, under a hole in the back cover. Press it with an unbent paperclip through a channel in case-back.
The button shorts the core board's RST (NRST) pin to GND (the RST contact is on the core-board header). This is a true hardware reset of the STM32: the processor restarts and goes through the BIOS boot again. A 100 nF capacitor to GND next to the button suppresses bounce.
Do not use boost #2 EN for reset: with EN = LOW a plain asynchronous boost still passes VBAT − 0.3 V, the core board stays at 3.4–3.9 V, and nothing resets.
The board has an unpopulated footprint for a load switch on the boost #2 output, in case a full power cut-off (not just a processor reset) is needed.
The ESP32 does not restart when the STM32 is reset. On start-up the BIOS re-initialises the SPI4 link to it by itself.
case-back.stl does not yet have the paperclip hole and channel. They need to be added (see Case changes).

VS1003B MP3 module

The mainboard has a place for a VS1003B module. The pins are reserved in the firmware; there is no driver yet.

VS1003B signal	STM32	Mode	Where on the core board
SCK	PI1	SPI2_SCK, AF5	only on the "LCD interface" connector, FPC23
MISO (SO)	PC2	SPI2_MISO, AF5	header R10.1
MOSI (SI)	PC3	SPI2_MOSI, AF5	header R10.2
XRST	PI2	output, pull-up, HIGH	only on the "LCD interface" connector, FPC22
XCS	PI3	output, pull-up, HIGH	header R21.1
XDCS	PI4	output, pull-up, HIGH	header R23.1
DREQ	PI8	input, pull-down	header R16.2

PI1 and PI2 are only on the core board's "LCD interface" connector, so the mainboard needs access to that connector (see Display).
The VS1003B volume is set over SPI with the SCI_VOL register; no separate analog volume control is needed.
The module's supply and form factor (which module board exactly, 3.3 V or 5 V) are TBD.
The analog output is mixed with the STM32 DAC, see Audio.

Audio

 PA4 (DAC1_OUT1) ─ RC LPF ─ 1 µF ─ 10 kΩ ─┐
                                          ├──► LIN  PAM8406
 VS1003B LOUT ─────────── 1 µF ─ 10 kΩ ───┘

 PA5 (DAC1_OUT2) ─ RC LPF ─ 1 µF ─ 10 kΩ ─┐
                                          ├──► RIN  PAM8406
 VS1003B ROUT ─────────── 1 µF ─ 10 kΩ ───┘

 5 V (boost #1) ── L ──┬── VCC PAM8406
                       C (electrolytic + ceramic)
                       GND (star)

Passive mixing per channel: each source (the STM32 DAC and the VS1003B line output) goes through a ~1 µF coupling capacitor and a ~10 kΩ resistor into the PAM8406 input of its channel.
The coupling capacitors are required. The VS1003B outputs sit at a DC bias, and so does the STM32 DAC output (mid-scale). Without the capacitors the sources drive DC current into each other.
1 µF / 10 kΩ are starting values. The 10 kΩ resistors and the amplifier input impedance attenuate the signal; set the final values on a prototype.
RC low-pass filter on the DAC outputs (starting value about 1 kΩ + 10 nF, cut-off about 16 kHz): the DAC runs at 22 050 Hz, and the filter smooths the steps.
LC filter on the amplifier supply: an inductor (starting value 10–47 µH, ≥ 1 A) + an electrolytic (about 220 µF) and a 100 nF ceramic at the amplifier pins.
Star ground: run the amplifier power ground straight to the common point at the power modules; run the signal ground to the core board GND. Route the analog section away from the boosts and the display CLK.
The power-up sequence (PE4 only after the DAC reaches mid-scale) stays as it is today, see power.md.

Display

33 Ω series resistors on CLK (PG7) and the sync lines HSYNC (PC6), VSYNC (PI9), and also on DE (PF10), at the STM32 end.
The RGB565 bus (R3–R7, G2–G7, B3–B7) runs on the front layer over the solid ground of the back.
How the mainboard connects to the panel and to the core board's "LCD interface" connector (a 40-pin 0.5 mm FPC connector on the board instead of two adapters with a folded ribbon, or something else) is TBD. When routing, take into account the pin-number mirroring described in pinout.md: the mainboard connector must join signals by function.
The same "LCD interface" connector also carries the buttons PH9–PH12, PI5, PI6, PI7, PI10, and PI1/PI2 for the VS1003B.

New STM32 signals

Besides the existing pinout (pinout.md), the board needs:

Signal	Direction	STM32 pin	Status
VBUS sense	input (through a divider)	PA9	decided
USB D− / D+	USB FS	PA11 / PA12	decided (how to reach the core board: TBD)
TUSB320 INT/ID	input	TBD
OTG_EN (gate of the VBUS P-MOSFET switch)	output	TBD
Charger board CE (charging disabled during OTG)	output, or in hardware from OTG_EN	TBD
Microphone	ADC input	TBD (not PA9)
Hard reset	core board NRST (header RST contact)	—	decided

The free pins are listed in pinout.md → Free pins. Earlier plans: PA1 (wake-up button), PD12 (vibration motor, TIM4_CH1), PD13 (LED, TIM4_CH2).

Case changes

Part	Change	Status
`case-back.stl`	paperclip hole and channel to the hard reset button	must be added, not in the current STL
`case-top.stl` or `case-back.stl`	cut-out for the external USB-C (position TBD; on the current build the USB-C is at the bottom edge)	TBD
`base-plate.stl`	not needed: the PCB replaces it

Files

KiCad project (in progress, link TBD).
STEP model of the board: opens in FreeCAD. The KiCad project opens in FreeCAD with the KiCad StepUp workbench.
Ways to make the board: CNC milling, toner transfer and etching, plotter-drawn resist and etching, or a finished board ordered from the author. Which of these suit a two-layer board is TBD.

Open questions

SS34 or a P-MOSFET ideal diode on the charging input.
TUSB320 variant and its support circuit; whether I2C is needed.
GPIOs for TUSB320 INT/ID, OTG_EN, charger CE and the microphone.
Whether the charger board has an accessible CE pin; whether to switch to a charger IC directly on the board.
How to bring USB D+/D− to PA11/PA12 of the core board.
Where to take EN from on the boosts; whether a boost with load disconnect is needed for a clean cut-off of the 5 V rail.
Final values for the mixing, RC and LC filters.
The exact VS1003B module, its supply and footprint.
The connection to the panel and to the "LCD interface" connector.
Module socket height (≤ 9.4 mm under the back cover).
Board thickness: 1.6 mm versus 1.5 mm for the base plate.
How the core board's BAT (VBAT) pin is connected, see power.md.

Core8Bit mainboard (in development)

Contents#

Concept#

Geometry#

Layers#

Board blocks#

USB-C: charging and OTG#

Charging input#

OTG: power for the connected device#

CC: TUSB320 in DRP mode#

Data#

PA9: VBUS sensing#

Hard reset#

VS1003B MP3 module#

Audio#

Display#

New STM32 signals#

Case changes#

Files#

Open questions#

Contents